CLK_XTAL_SEL=XTAL16M, CLK_OSC32M_DIV=BY1, SYS_CLK_SEL=CLK_OSC, CLK_WDT_SEL=CLK_WDT_SEL_32K, CLK_32K_SEL=XTAL32K, CLK_BLE_SEL=CLK_BLE_SEL_8M
system clock source and divider register
| APB_DIV | APB_CLK = AHB_CLK/(APB_DIV+1) |
| AHB_DIV | AHB_CLK = SYS_CLK / (AHB_DIV+1);Note Before enable BLE clock (CLK_BLE_EN =1) It is mandatory to set AHB_CLK = 32 or 16 or 8 MHz. |
| CLK_BLE_SEL | BLE frequency indicator 0 (CLK_BLE_SEL_8M): BLE run at 8M 1 (CLK_BLE_SEL_16M): BLE run at 16M |
| CLK_WDT_SEL | Select Watch Dog clock 0 (CLK_WDT_SEL_32K): watch dog run at 32K 1 (APB): watch dog run at APB clock |
| CLK_XTAL_SEL | Crytal clock selection 0 (XTAL16M): external crystal is 16M 1 (XTAL32M): external crystal is 32M |
| CLK_OSC32M_DIV | digital OSC clock input selection 0 (BY1): use original 32M RCO clock 1 (BY2): divide 32M OSC clock into 16M |
| CLK_32K_SEL | 32K clock source selection 0 (XTAL32K): digital 32K clock source is external 32K crystal 1 (RCO32K): digital 32K clock source is internal 32K RCO |
| CLK_XTAL_OE | system clock output enable |
| CLK_32K_OE | 32K clock output enable |
| XTAL_OUT_DIV | high frequency xtal clock output divider |
| CGBYPASS | If it is 0, it can save CPU power in active mode |
| SYS_CLK_SEL | Select SYS_CLK source 0 (CLK_OSC): 32M internal clock 1 (CLK_XTAL): external crystal clock 2 (CLK_32K): 32K clock |